1. Field of the Invention
This invention relates to a latch circuit and more particularly to a high performance latching circuit having an integrated set and reset capability.
2. Description of the Prior Art
Clocked latching circuits are well known in the prior art as bistable circuits having both clock and data signal inputs wherein the output is not altered from a given state until the occurrence of an input clock signal. It is often desirable to add a set and reset capability to such devices so that their output state can be placed at a known logical condition without having to provide an input clock signal. Typically, the set/reset capability is added at the cost of several circuit elements and additional power requirements. Further, the added logic elements require that a designer test for and resolve potential signal race conditions in order to be sure that the latch will switch when and as desired.